Technology Limits and Compact Model for SiGe Scaled FETs

نویسندگان

  • R. W. Dutton
  • C.-H. Choi
چکیده

Stress relaxation in strained-Si MOSFETs can be significant in the presence of compressive stress imposed by trench isolation, especially for highly scaled active regions. Stress of the strained region is reduced by ∼2/3 when the active region is scaled from Lactive=0.4 μm to 0.1 μm. Mobility can be lower by 50 % for narrow active widths resulting from the strain relaxation. The strain relaxation may restrict the use of strained-Si MOSFETs for technology nodes beyond 25 nm. Electrical and thermal characteristics of strained-Si devices are investigated and a compact junction capacitance model for strained-Si MOSFET suitable for circuit simulation is proposed.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Monte Carlo Investigation of Optimal Device Architectures for SiGe FETs

Strained silicon channel FETs grown on virtual SiGe substrates show clear potential for RF applications, in a material system compatible with silicon VLSI. However, the optimisation of practical RF devices requires some care. 0.1-0.12pm gate length designs are investigated using Monte Carlo techniques. Although structures based on 111-V experience show fT values of up to 94 GHz, more realistic ...

متن کامل

Atomistic approach to study charge and current distribution in ultra - scaled

Submitted for the MAR10 Meeting of The American Physical Society Atomistic approach to study charge and current distribution in ultra-scaled SiGe/Si core/shell nanowire FETs ABHIJEET PAUL, SAUMITRA MEHROTRA, MATHIEU LUISIER, GERHARD KLIMECK, Purdue University — Recent development in the fabrication processes have enabled the manufacturing of ultra-scaled, high mobility SiGe/Si core/shell nanowi...

متن کامل

Nanoscale CMOS Modeling

Nanoscale CMOS Modeling by Mohan Vamsi Dunga Doctor of Philosophy in Engineering Electrical Engineering and Computer Sciences University of California, Berkeley Professor Ali M. Niknejad, Chair Since its inception almost four decades ago, the conventional planar bulk silicon MOSFET has been scaled relentlessly in accordance with the Moore’s Law. However, as the state-of-the-art MOSFET makes inr...

متن کامل

Quantum capacitance in scaled down III-V FETs Citation

We have built a physical gate capacitance model for III-V FETs that incorporates quantum capacitance and centroid capacitance in the channel. We verified its validity with simulations (Nextnano) and experimental measurements on High Electron Mobility Transistors (HEMTs) with InAs and InGaAs channels down to 30 nm in gate length. Our model confirms that in the operational range of these devices,...

متن کامل

Quantum Capacitance in Scaled-Down III-V FETs

We have built a physical gate capacitance model for III-V FETs that incorporates quantum capacitance and centroid capacitance in the channel. We verified its validity with simulations (Nextnano) and experimental measurements on High Electron Mobility Transistors (HEMTs) with InAs and InGaAs channels down to 30 nm in gate length. Our model confirms that in the operational range of these devices,...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1995